EVALUATION OF FAULT MITIGATION TECHNIQUESFOR NEUROMORPHIC HARDWARE ACCELERATOR - EXPRO PLUS

Objective: To analyse the impacts of fault propagation in spiking neural networks (SNN), propose design mitigation techniques, identify relevant neuromorphic IPs and select a baseline concept for implementation.Description: Future missions, including planetary landing, planetary exploration, docking, debris removal, space situational awareness, in-orbit servicing, etc. will need increased autonomy to address latency issues. This autonomy will rely on AI-driven computer vision and advanced computing capabilities. However,traditional neural network inferences typically require hardware platforms such as FPGAs or GPUs, which may consume anywhere from afew tens of watts to 100 watts. This high-power consumption may necessitate active cooling systems, impacting weight, volume, complexity, and ultimately resulting in additional costs and risks for missions. Safety-critical class 1 missions, including autonomous docking, autonomous landing, and autonomous rover/drone navigation, will require lower power, low footprint (pin count), scalable, and fault-tolerant hardware accelerators. Event-based processing with Neuromorphic technologies, show potential for the future of intelligent sensing, whether it involves event-based cameras, LiDAR, or radar sensors. Neuromorphic technology can address in an effectivemanner the challenge posed by edge AI, sustaining a high processing load, while keeping power consumption low (from few Watts to sub-Watt). Concrete use cases such as, autonomous landing, autonomous docking have been studied, validating Neuromorphic technology through the deployment on commercial device (COTS). Neuromorphic technology is suited for computer vision applications, planned activities should also confirm the suitability for radar as well. Few commercial IPs have shown potential in studies as explained above.However, additional work is needed to adapt a solution for space missions, ensuring low power, scalability, low pin count, and fault tolerance. Leveraging state-of-the-art neuromorphic commercially available IPs, this activity aims to propose a solution that addresses these needs effectively by designing a neuromorphic hardware accelerator using advanced rad hard ASIC technology. This activity encompasses the following tasks: - Hardware accelerator specifications consolidation - selection and product roadmap definition - IP fault mitigation techniques analysis - Hardware accelerator architecture definition - Hardware accelerator design - Hardware accelerator validation / simulation.Procurement Policy: C(1) = Activities in open competition limited to the-non-Large-System Integrators.For additional information please go to:http://www.esa.int/About_Us/Business_with_ESA/Small_and_Medium_Sized_Enterprises/Opportunities_for_SMEs/Procurement_policy_on_fair_access_for_SMEs_-_the_C1-C4_Clauses